The inventive concept relates to an internal supply voltage generator and a semiconductor device having the same, and more particularly, to an internal supply voltage generator capable of reducing latch-up and a semiconductor device having the same.
In general, a semiconductor device includes an internal supply voltage generator that receives an external supply voltage and generates various internal supply voltages from the external supply voltage. For example, if the internal supply voltage generator is included in a driving circuit that drives a display device, e.g., a liquid crystal display (LCD), the internal supply voltage generator generates various internal supply voltages for driving the display device. Since the internal supply voltage generator independently generates voltages used in a semiconductor device, it is important to generate stable internal voltages regardless of a change in temperature, processes, or pressure.
If a semiconductor device operates in response to an internal supply voltage from the internal supply voltage generator, latch-up occurs according to the operating characteristics of the semiconductor device. Here, latch-up is a phenomenon that a current path is formed between a supply voltage source and a ground voltage source due to a parasitic bipolar transistor component generated in a device, thereby causing over-current to flow. Latch-up causes the device to be damaged or to malfunction.
FIG. 1 is a cross-sectional view of a general semiconductor circuit. In more detail, FIG. 1 illustrates an NMOS transistor and a PMOS transistor of a complementary metal-oxide semiconductor (CMOS) inverter 10, as an example of the general semiconductor circuit
As illustrated in FIG. 1, the CMOS inverter 10 is fabricated by forming a P-well 12 and an N-well 13 in a P-type substrate 11. In the P-well 12, N-type impurities are formed to obtain the NMOS transistor. An electrode is disposed between the N-type impurities to receive an input signal IN. A ground voltage VSS is applied to one of the N-type impurities, and the other N-type impurity is connected to an output terminal for delivering an output signal OUT. In the P-well 12, a P-type impurity is further formed to apply thereto a predetermined low voltage, for example, a low voltage VL that is less than the ground voltage VSS.
In the N-well 13, P-type impurities are formed to obtain the PMOS transistor. An electrode is disposed between the P-type impurities to receive the input signal IN. A supply voltage VDD is applied to one of the P-type impurities, and the other P-type impurity is connected to an output terminal for delivering the output signal OUT. In the N-well 13, an N-type impurity is further formed to apply thereto a predetermined high voltage, for example, a high voltage VH that is greater than the supply voltage VDD.
In the CMOS inverter 10, parasitic transistor components that correspond to a PNP-type bipolar transistor and an NPN-type bipolar transistor are generated as will be described in detail with reference to FIG. 2.
FIG. 2 is a circuit diagram of parasitic transistors formed in the CMOS inverter 10 of FIG. 1. As illustrated in FIG. 2, the parasitic transistors include a PNP-type bipolar transistor T1 that is connected between a supply voltage source VDD and a low voltage source VL, and an NPN-type bipolar transistor T2 connected between a high voltage source VH and a ground voltage source VSS. Also, a collector of the PNP-type bipolar transistor T1 is connected to a base of the NPN-type bipolar transistor T2, and a base of the PNP-type bipolar transistor T1 is connected to a collector of the NPN-type bipolar transistor T2.
The PNP-type and NPN-type parasitic transistors T1 and T2 illustrated in FIG. 2 may be forward biased or reverse biased according to voltages applied to electrodes of the PNP-type and NPN-type parasitic transistors T1 and T2. When the PNP-type and NPN-type parasitic transistors T1 and T2 are turned on by applying a voltage thereto in a forward direction, over-current flows through them due to latch-up.
An internal supply voltage generating circuit that includes a multi-stage booster circuit, and thus, is capable of sequentially generating internal voltages, has been widely used as an example of an internal supply voltage generating circuit generating a plurality of internal voltages. If the internal supply voltage generating circuit that employs a multi-stage booster circuit applies internal voltages to the CMOS inverter 10 of FIG. 1, a high internal voltage VH and a low internal voltage VL are sequentially generated and provided at predetermined intervals of time. Thus, a probability that the PNP-type and NPN-type parasitic transistors T1 and T2 will be turned on is increased more than when the multi-stage booster circuit is not employed.
Thus, when an internal supply voltage generating circuit that employs a multi-stage booster circuit is used in a semiconductor device, latch-up is more likely to occur in a semiconductor device than when the multi-stage booster circuit is not employed.